Senior Design Engineer sought by ARM Inc. in Austin, TX to assist the design team to ensure the RTL design meets all functional requirements. Min Req: Master's Degree in Electrical Engineering, Computer Engineering or a related program and 4 years' experience in design verification of multiple functional blocks; developing SystemVerilog UVM testbenches for block-level functional verification of units within the Coherent Mesh Network and Memory Controller; creating and maintaining detailed verification plans and generating and running test cases on logic simulation models; creating test harnesses and methodologies using interpreted languages; microarchitecture modeling and designing microarchitecture concepts such as processor pipelines, coherent memory hierarchy, and system interconnect; Debugging functional errors in the RTL model using simulation tools and debug tools; and, developing virtual platform models (VPMs) using transaction-level models (TLMs) in a SystemC-based framework.Send resume to: email@example.com. Reference #2007
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